
List Of Figures
System Reference, January 2001
13
Figure 60 Relation Between Load Capacitance and Voltage Ripple - Range 1m
148
Figure 61 Relation Between Load Capacitance and Voltage Ripple - Range 2
149
Figure 62 Relation Between Load Capacitance and Voltage Ripple - Range 3
m
149
Figure 63 Relation Between Load Capacitance and Voltage Ripple - Range 4
m
150
Figure 64 Measurement Block Diagram 151
Figure 65 Load regulation in performance range 1 151
Figure 66 Load regulation in performance range 2 152
Figure 67 Load regulation in performance range 3 152
Figure 68 Load regulation in performance range 4 153
Figure 69 C-overload performance in range 2 153
Figure 70 Vbump Trigger Paths and Function 156
Figure 71 Voltage settling, load capacitance 100nF 157
Figure 72 Voltage settling, load capacitance 100µF 158
Figure 73 Voltage step, high load (quadrant 1) 158
Figure 74 Ganged DPS Connections 161
Figure 75 DPS Connections 163
Figure 76 Device Operation Sequence 164
Figure 77 Measurement Operation Sequence 165
Figure 78 High Current DPS Block Diagram 170
Figure 79 Analog Waveform Generation 185
Figure 80 High Speed AWG and High Resolution AWG Block Diagram 189
Figure 81 Output Routes (Single-ended) 190
Figure 82 Output Routes (Differential) 191
Figure 83 DC Routes 192
Figure 84 Loop Back Routes 193
Figure 85 Ultra High Speed AWG Block Diagram 196
Figure 86 Output Routes (Single-ended) 197
Figure 87 Output Routes (Differential) 198
Figure 88 DC Routes 199
Figure 89 Loop Back Routes 200
Figure 90 Real-Time Digitizing 204
Figure 91 Coherent Sampling 205
Figure 92 Digitizer Block Diagram 208
Figure 93 Input Resistance 210
Figure 94 DC Routes 211
Figure 95 Loop Back Routes 212
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