AWG G3 PAD FOR PS3 Spezifikationen PDF herunterladen (Seite 222)

7 Analog Modules Sampler

222 System Reference, January 2001

Loop Back Routes

The input multiplexer can make the loop back route

between adjacent pogo pins (A+ and B+, or C+ and D+).

When a loop back route is made, the loop back route is

disconnected from other routes. Hence, you can make

multiple loop back routes, or also make a loop back route

and another route (output route or DC route) using other

pins at the same time. In the following figure, the possible

loop back routes are represented with bold lines.

Figure 100 Loop Back Routes

The loop back route is designed so that the line impedance

becomes 50 ohm exactly. As a result, the bandwidth of the

loop back route extends up to 500 MHz (typical value).

Hence, by using the loop back route, you can make a route

that has better performance than using user relays for

changing the connections in the test circuit.

A+

(Ch1 Input A)

Timing

Generator

B+

(Ch1 Input B)

C+

(Ch2 Input A)

D+

(Ch2 Input B)

SYNC CLK

Pogo Pin

smpl3

Master Clock

SYNC DATA

Channel

Multiplexer

Sequencer/

Waveform

Memory

Sampler Unit

ADC

Input

Multiplexer

Clock Distributor

DC offset

AGND

DGND

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